Historically, the demands of microprocessor technology have been increasing at a faster rate than the support technologies, such as DRAM and TTL/programmable logic. Recent trends are further aggravating this mismatch in the following ways. First, microprocessor clock rates are rapidly approaching, and in some cases exceeding, the clock rates of standard support logic. In addition, the clocks per instruction rate is rapidly decreasing, putting a very high bandwidth demand on memory. Newer designs such as RISC architectures, are demanding evermore memory bandwidth to accomplish the same amount of work. The memory bandwidth demand has been further aggravated by the need for direct memory access (DMA) by devices such as coprocessors and multi-processors. Finally, the rate at which new devices are being introduced into the market place is accelerating-further exacerbating all of the above.
As a result of these trends, two severe performance bottlenecks have emerged that continue to influence the way that systems are designed. Memory bandwidth, as a performance limiter, has already forced the use of cache memories in many microprocessors systems. By way of example, the use of cache memories is common place in the 80386.TM. generation of microprocessors manufactured by Intel Corporation. Also, Intel's 80486.TM. and i860.TM. (also referred to as the i860XP.TM.)processors include on-chip caches for enhanced performance. It is clear that further changes in the memory hierarchy (primary cache, secondary cache, DRAM architectures, etc.) will be required to sustain performance increases in future generations. (Intel, 80386, 80486, i860, and i860XP.TM. are all trademarks of Intel Corporation.)
Another performance bottleneck is the clock rate and input/output (I/O) timings. It has become apparent that the investment required to continue increasing the microprocessor clock rate (and the resulting I/O timings) cannot be sustained across all components in the system. Even if one could afford the investment, the schedule impact of coordinating with possibly many vendors, could easily make such an architecture non-competitive. These factors have already forced the use of asynchronous interfaces to isolate the frequency scaling problem to a subset of the system components. In the future, it is clear that high speed CPU interfaces will need to be designed around an even more tightly controlled specification in order to reach the desired level of performance.
Exemplary of the prior art, Intel's 80385 cache SRAM memory is typical of past approaches. To begin with, one of the chief drawbacks associated a 80385 like SRAM array is its inability to support concurrent operations at both the CPU and memory interfaces. That is, for every access to the read/write storage array, only one piece of data gets transferred. This means that when coupled to the 80486, for example, a cache line read operation requires four separate transfers. In other words, the SRAM array needs to be accessed repeatedly to obtain each piece of the cache line, severely limiting the clocks available to the memory interface. Alternatively, a wide bank of SRAMs could be employed along with corresponding external multiplexers, but only at the expense of additional complexity and cost.
Another common drawback of prior art cache memories is that every transfer is required to be synchronized. In other words, as data arrives at the cache from the memory bus, before that data can be transferred to the CPU bus, a handshake must occur with the microprocessor. This process must be repeated for the next data segment to be brought in from the memory bus. Note that this is simply another way of stating that the transfer of data between the memory and CPU buses requires synchronous operations. Such operation presents a serious burden on the computer system's performance as CPU clock rates increase.
The present invention discloses an integrated cache controller employed within a second level cache memory system for multiprocessor systems. It is intended to work cooperatively with a CPU unit such as the Intel 80486 or i860XP.TM. processors, with cache memory as disclosed in a co-pending application entitled, "Integrated Cache SRAM Data Path" and with a memory bus controller (MBC) for adapting the second level cache controller to a wide range of memory bus protocols such as disclosed in a co-pending application entitled, "Second Level Memory Bus Controller Unit" which applications are assigned to the assignee of the present invention.